10-16-2014, 07:43 PM -
Hey all ...
Well.. let me first tell that I already read all stuff about words on the air and about doing some POC before post
.
But I'm with that idea on my mind for a good amount of time, and I don't had already read too much line of code from rpcs3. This is more about a brain storm, where I don't know exactly what to do;
Okay... so. All those discussions were about how to fetch, transcode, interpret etc etc from Cell instruction set to x86. Good... If I'm right .. all that workload is done by CPU, and GPU is used only for OpenGL as backend. Is that right?
What I'm raising here is just an organization and architecture idea that comes ... anyway... Direct to the point, if a part of ISA is *executed* on the GPU, majority(or only or part of) the SIMD ones dispatched to SPE? It can be cached until X number of instructions then dispatched to GPU.
I'm not saying that it's better or easily done... I'm just raising the idea: "If some workload is done by OpenCL on the GPU. Releasing or reducing the workload on CPU". And I know all the problems to access memory outside GPU, the gap between dispatch and execute per instruction or per block of instructions.
I have little HPC experience on hybrid cluster, using OpenMP and OpenCL(for the fun..even it were a financed project by my university :}) , and *maybe* some thing can be reached dividing the workload on CPU and GPU for emulation purpose.
Right now I'm reading "Emu / CPU /", "Emu / Cell /" and "Emu / Memory" .. so I'm posting that before actually understand all the code... because I will do that on my extra free time ^^...and it can take some days.
Well, thanks
Well.. let me first tell that I already read all stuff about words on the air and about doing some POC before post
.But I'm with that idea on my mind for a good amount of time, and I don't had already read too much line of code from rpcs3. This is more about a brain storm, where I don't know exactly what to do;
Okay... so. All those discussions were about how to fetch, transcode, interpret etc etc from Cell instruction set to x86. Good... If I'm right .. all that workload is done by CPU, and GPU is used only for OpenGL as backend. Is that right?
What I'm raising here is just an organization and architecture idea that comes ... anyway... Direct to the point, if a part of ISA is *executed* on the GPU, majority(or only or part of) the SIMD ones dispatched to SPE? It can be cached until X number of instructions then dispatched to GPU.
I'm not saying that it's better or easily done... I'm just raising the idea: "If some workload is done by OpenCL on the GPU. Releasing or reducing the workload on CPU". And I know all the problems to access memory outside GPU, the gap between dispatch and execute per instruction or per block of instructions.
I have little HPC experience on hybrid cluster, using OpenMP and OpenCL(for the fun..even it were a financed project by my university :}) , and *maybe* some thing can be reached dividing the workload on CPU and GPU for emulation purpose.
Right now I'm reading "Emu / CPU /", "Emu / Cell /" and "Emu / Memory" .. so I'm posting that before actually understand all the code... because I will do that on my extra free time ^^...and it can take some days.
Well, thanks